RF IC design also gives performance requirements and constraints on key parameters such as noise diagrams, power, phase noise, harmonics, linearity, etc. in the form of a "system budget ", etc. this budget is determined by the system-level design team and passes budget constraints and performance requirements to the rf designer responsible for each module in the system diagram. these topologies and circuits undergo an iterative process of design, simulation, optimization, and layout simulation using electromagnetic simulation tools capable of handling IC.


　　design constraint

　　Because some on-chip passive devices (e.g., inductors and capacitors) are severely limited by the manufacturer, RF IC designers often have limited control over the dimensions and values of these components. this leads to greater uncertainty in the design and may require repeated processes with the plant to design and test new components to produce components that best meet RF circuit requirements.

　　In some cases, rf designers may require additional modeling of bondwire and other vendor-independent packaging dynamics to accurately predict final device performance in parasitic and terminal assembly. Many RFIC are delivered in the form of bare sheets and are bound directly to components or trays rather than typical IC packages and PCB stickers.

　　Electromagnetic simulation

　　Once the RF IC enters the physical layout stage, many iterations of EM simulation, circuit simulation and parasitic extraction are usually carried out, which involve at least IC encapsulation, but may also take into account the PCB and external circuits of the device. The reason is that the RF circuit is very similar to the highly sensitive analog circuit, and the performance may change greatly due to the peripheral external circuit, electric / magnetic field, temperature, electromagnetic signal and other environmental factors.

　　Even after streamer testing, testing, model enhancement, and additional optimization are often required before the final design and production RFIC are submitted.

　　RF IC Design Process

　　Design specification

　　Specifications

　　Constraints

　　Topologies

　　Test bench development

　　System design

　　High-level system design and budgeting

　　Behavioral modeling

　　Circuit Synthesis

　　HDL Mixed-level SIM

　　Mixed-level partitioning

　　Circuit Design

　　Use of foundry design kit

　　Spiral inductor synthesis/modeling

　　Detailed circuit design

　　Circuit Simulation

　　Time domain

　　Frequency domain

　　Physical Design

　　Extraction of on-chip passives

　　Extraction of package parasitics

　　Layout

　　Electromagnetic simulation and extraction

　　Parasitic extraction

　　Design rules check (DRC)

　　Layout versus schematic (LVS)

　　Verification in systems test bench

　　Sign-off Net extraction/Tape-out